| 词汇 | cache-line |
| 释义 | BETA cache linecollocation in Englishmeanings of cacheand lineThese words are often used together. Click on the links below to explore the meanings. cache noun uk /kæʃ/ us /kæʃ/ a hidden store of things, or the place where they ... See more at cache line noun uk /laɪn/ us /laɪn/ a long, thin mark on the surface ... See more at line Examples of cache linecache line A cacheline consists of many cells, and we have assumed that the whole line would be transferred. Note in addition that the transaction latencies are kept constant despite varying the cacheline size. Finally, how is speedup affected by network latency and cacheline size? The design issue of cacheline size is particularly important. Such machines require each writable cacheline to have a single owner. This will cost perhaps five cycles per frame (assuming the frame size is roughly half the cacheline size, and a 10-cycle miss penalty). Each cacheline is in one of the following states: dirty (has been updated by local processor), valid, invalid or shared. From Wikipedia This example is from Wikipedia and may be reused under a CC BY-SA license. Later, when the cacheline is evicted, 16-bit writes are used, thus eliminating all 8-bit writes over the bus. From Wikipedia This example is from Wikipedia and may be reused under a CC BY-SA license. A data cache typically requires two flag bits per cacheline a valid bit and a dirty bit. From Wikipedia This example is from Wikipedia and may be reused under a CC BY-SA license. For any given pair of caches, the permitted states of a given cacheline are listed in the table on the right. From Wikipedia This example is from Wikipedia and may be reused under a CC BY-SA license. A demand fetch for the missing instruction or data cacheline is generated if necessary. From Wikipedia This example is from Wikipedia and may be reused under a CC BY-SA license. Similarly, a write-set conflict occurs if a cacheline in the write-set is read or written by another thread. From Wikipedia This example is from Wikipedia and may be reused under a CC BY-SA license. Cacheline toggle and cacheline wrap modes are two forms of critical-word-first cacheline fetching. From Wikipedia This example is from Wikipedia and may be reused under a CC BY-SA license. As with other cache coherency protocols, the letters of the protocol name identify the possible states in which a cacheline can be. From Wikipedia This example is from Wikipedia and may be reused under a CC BY-SA license. To prevent this, every cache controller monitors the bus, listening for broadcasts which may cause it to invalidate its cacheline. From Wikipedia This example is from Wikipedia and may be reused under a CC BY-SA license. These examples are from corpora and from sources on the web. Any opinions in the examples do not represent the opinion of the Cambridge Dictionary editors or of Cambridge University Press or its licensors. |
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